ARM treats FIQ(Fast interrupt request) at a higher priority as compared to IRQ(interrupt request). When an IRQ is executing an FIQ can interrupt it while vice versa is not true.
ARM uses a dedicated banked out register for FIQ mode ; register numbers R8-R12.
http://learnlinuxconcepts.blogspot.in/2014/06/arm-architecture.html
So when an FIQ comes these registers are directly swapped with the normal working register and the CPU need not take the pain of storing these registers in the stack. So it makes it faster.
One more point worth noting is that the FIQ is located at the end of exception vector table(0X1c) which means that the code can run directly from 0X1C and this saves few cycles on entry to the ISR.
For any clarifications or if you have any suggestion please post comments below.
ARM uses a dedicated banked out register for FIQ mode ; register numbers R8-R12.
http://learnlinuxconcepts.blogspot.in/2014/06/arm-architecture.html
So when an FIQ comes these registers are directly swapped with the normal working register and the CPU need not take the pain of storing these registers in the stack. So it makes it faster.
One more point worth noting is that the FIQ is located at the end of exception vector table(0X1c) which means that the code can run directly from 0X1C and this saves few cycles on entry to the ISR.
For any clarifications or if you have any suggestion please post comments below.
